Recent changes to feature-requests

Save and Restore simulation state

2024-08-02T06:23:25.345000Z

Hi,
I want to save the simulatiion state. then later restore it and resume the simulation, similar to the one found in verilator ( https://veripool.org/guide/latest/simulating.html?highlight=save#save-restore ), but I couldn't find a feature that'll support this in iverilog. Could you suggest a way in which this can be done in iverilog.

Thanks,
Arunesh

#52 IVL_UVM: UVM support - incremental additions

2020-11-26T17:11:16.974000Z

Hi Srini,

We normally only use SourceForge for the mailing list and for release distribution. I think Steve requested you to use to discuss this on the mailing list. Please post this to the iverilog-devel mailing list.

The short answer is look at ivtest which is our regression environment and determine how to integrate your tests into that environment. For your development I completely understand your desire to have your tests Makefile driven and it should be possible to architect your tests so they work in both the Makefile and ivtest environment. We do make changes to ivtest from time to time, but the basic test flow has been stable for a very long time. The one thing I would like to change is add parallel testing support which in concept should be fairly straight forward except there is one VHDL test the violates the unwritten rule "no test should depend on a previous tests output."

IVL_UVM: UVM support - incremental additions

2020-11-26T15:41:30.028000Z

Hello,
I would like to add UVM support to Icarus. I have been working with few interns to add simple features with Icarus. Will soon add code to a GitHub repo and send a link.

One challenge we see is that unit tests work, larger UVM code base (not really full UVM, but just many classes/objects) tend to break the tool. I wonder how to submit such testcases when they are spread across files, has a Makefile etc. I am sure this is possible, just want to understand how you folks do it here.

Please share your thoughts on this.

Looking forward to update, maintain and contribute to IVL_UVM!

Regards
Srini

#51 VHDL: rotate support for simulation

2017-12-08T16:18:59.132000Z

You need to clock on the edit link. I updated it to VHDL since I assume that is what you were trying to do.

#51 VHDL: rotate support for simulation

2017-12-08T16:18:12.027000Z

summary: rotate support for simulation --> VHDL: rotate support for simulation

#51 rotate support for simulation

2017-12-06T17:37:12.081000Z

It currently won't let me edit the title. Should I cancel this one and do another ticket?

#51 rotate support for simulation

2017-12-06T06:37:03.771000Z

Is this for VHDL? If so please add VHDL to the beginning of the title.

rotate support for simulation

2017-12-04T22:09:15.252000Z

I'd love to have the rotate_left, rotate_right functions available. They don't synthesize well unless using a constant, but they could easily be converted as:

assign A_out = (A_in << bits_to_rotate) | (A_in >> (~bits_to_rotate+1));

for a rotate left (sample from stackoverflow). This could at least create a simulatable rotate.

VHDL: rotate support for simulation

2017-12-04T22:09:15.252000Z

Ticket 51 has been modified: VHDL: rotate support for simulation
Edited By: Cary R. (caryr)
Summary updated: u'rotate support for simulation' => u'VHDL: rotate support for simulation'

Arrays in port declarations

2015-11-20T13:04:19.670000Z

Using arrays in module in/outputs fails: module test(input wire [7:0] x[0:2]);

assert: elaborate.cc:6242: failed assertion netnet->pin_count()==1