Version 1.5 Released

aghoras — Mon, 14 May 2018 15:55:15 -0000

Added support the following VHDL-2008 support:
- Package and subprogram generics.
- Generic types, subprograms and packages.
- Added support for force/release keywords
- Added support for hierarchical signal access
- Added support for context definition and refernce

Vesion 1.2.2 Released

KOBAYASHI Tadashi — Wed, 04 May 2016 08:14:26 -0000

Version 1.2.2 is same with the development build 1.2.1.c on November 2015.

This release includes some Verilog features:
- Add AutoEditStrategy for Verilog multi-line comment.
- Exactly matching for occurrence marker in Verilog.
- Add write occurrence marker in Verilog.
- Update outline database when selection is changed for occurrence marker.

Vesion 1.2.1 Released discussion

ILLICO — Wed, 06 May 2015 07:33:40 -0000

Thanks for this new version.
Now Altera encrypted files are supported, then scan completed at 100%.
Tested on Eclipse Luna SR2

Vesion 1.2.1 Released

KOBAYASHI Tadashi — Tue, 05 May 2015 14:35:36 -0000

Version 1.2.1 was built and tested on Eclipse Luna SR2.

This release includes:
- Added some Verilog syntax checks.

From Sjors Hettinga:
- Ignoring encrypted Verilog code, based on the protected pragma.
- Using the used VHDL packages in a file, when jumping to a declaration of this value in a package.
- Upon VHDL detection of multiple implementations of the item you want to jump to.
- VHDL various syntax checks.

Vesion 1.2.0 Released

aghoras — Mon, 01 Jul 2013 21:07:32 -0000

Version 1.2.0 is here. As of this release, all official builds will use Java 7.

This release includes:
From Illian Dinev:
Added support for subtype definition jumping.
Improved code info hit popup
Autocomplete of "use" with common ieee libraries
New templates for record, array and subtype

From Maximilian Girlich:
Improved New File Template selection (for Verilog and VHDL)
Improved formatting in VHDL (alignment on => := and directional directives)

VEditor 1.2 (Testing)

aghoras — Wed, 24 Apr 2013 18:25:08 -0000

VEditor 1.2 is available via the testing update site. See the bottom of You can also put the main wiki page (sourceforge.net/apps/mediawiki/veditor/index.php?title=Main_Page) for information on how to get the latest testing version.

New Features:
+ Better association of build errors with source files
+ Better handling of direct VHDL instantiations in the outline
+ Ability to use variables in the compile/simulate/build commands

VEditor 1.1.1

KOBAYASHI Tadashi — Wed, 10 Apr 2013 13:03:14 -0000

The new version fixed some bugs and improved Verilog semantics checker.

Fixed format bug(ID 3553659)
Debug evaluation of parameter expression.
Stricter bit width checking of assignment and operation.
Checking input or output port connection.

VEditor 1.1.0

aghoras — Sat, 03 Nov 2012 08:23:35 -0000

The new version improves Verilog parser.

New Features:
* Verilog syntax check more strictly.
* Add waring preference page.
* Add waring annotation about the followings:
"never used", "never assigned", "cannot be resolved", "assignment bit width mismatch" and "blocking and non-blocking assignment"
* Calculate parameter and localparam value in annotation hover.

VEditor 1.0.0

aghoras — Mon, 12 Sep 2011 18:05:39 -0000

It's time for another release of the VEditor. Even though, the version is reved to 1.0.0, this is a routine release. It will however, make future test releases easier by not wasting an extra digit. If the Linux kernel can do it, so can we :). Thanks to Stijn and Silvio for their contributions.
Here’s the list of bug fixes:
* Multi-line tabbing problem (ID 2726346)
* VHDL parser hangs (BUG ID 2952670)
* when using autocompletion, files often get mixed line endings
* mismatch between the classes RecordElement and TypeDecl, making autocompletion of record members to malfunction
* Fixed VHDL parser errors (3034727, and 1835772)

New Features:
* Extended autocompletion to also include types, constants and function declarations in packages
* Extended the VHDL syntax to the 2002 standard using http://www.iis.ee.ethz.ch/~zimmi/download/vhdl02_syntax.html
* Now when the external builder has errors, and you save the file these errors disappear
because saving a file causes the file to be parsed internally (without errors) and removes all markers.
Adding a new marker type for problems/warnings of the external builder solves this issue.
(http://sourceforge.net/tracker/?func=detail&aid=3034746&group_id=103963&atid=636481)
* Default error parsers not stored in workspace anymore
* The VHDL parser now has time out options for large files.
* It is possible to skip parsing of VHDL parsing by including special comments (see the features page)
* Several internal improvements and code re-org
* VHDL auto test-bench creation now has its own customizable template (see the features page)

VEditor update and Testing Site

aghoras — Mon, 12 Sep 2011 18:04:27 -0000

The VEditor update and testing sites are operational again. See the Download section of the main page for details.

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