CAD Flow For Design and Verification

Complete flow to enable Reusable IP creation starting from RTL generation as applicable, run different flows like RTL compile with simulation tools, static checks for Lint, CDC ..., Synthesis(Lite) and Equivalence Check.

Supports multiple configuration of IP needed by the IP team(s)- configuration through parameters and `define .

Supports seamless integration of the IPs as per the needed configuration- no need for multiple delivery of that IP.

Supports multiple versions/configs of the same IP in a SOC or SubSystem.

Has hooks to facilitate integration of the IP with overrides while IP team delivers next release.

Has capability to create IP-XACT Components, RGISTERS,/MemoryMap .

Based upon the IP maturity, the IPQC is being run and eventually packaging and release.