User Activity

  • Posted a comment on ticket #817 on ngspice

    The latest patch fixes the bug when using the full original circuit. Thanks for the quick fix Giles.

  • Posted a comment on ticket #817 on ngspice

    If you have a patch, I can build and test locally.

  • Posted a comment on ticket #817 on ngspice

    You are right, the problem occurs when there are models at more than one level of the hierarchy. Here is a cut down version of the code that demonstrates the problem * Bug 817 test case .subckt 74LVC245APW OE IN OUT VCC GND .MODEL MNEN NMOS LEVEL = 3 KP = 154E-6 .MODEL MPEN PMOS LEVEL = 3 KP = 63.7E-6 .SUBCKT LVCINVAN 2 3 50 60 MP1 3 2 50 50 MPEN W= 30U L=0.8U AD=35P AS=35P PD=35U PS=30U MN1 3 2 60 60 MNEN W= 12U L=0.8U AD=30P AS=30P PD=20U PS=15U .ENDS XINV 30 35 50 60 LVCINVAN .ends .model MR1...

  • Created ticket #817 on ngspice

    Global models are not visible from with subcircuits

  • Modified ticket #1004 on Icarus Verilog

    Packages which tries to create an instance of a class is not accepted by Icarus.

  • Posted a comment on ticket #1004 on Icarus Verilog

    This is now fixed in the master branch.

  • Modified ticket #1031 on Icarus Verilog

    Parameters defined in package not seen in Verilog module imported it

  • Posted a comment on ticket #1031 on Icarus Verilog

    This is now fixed in the master branch. The fix is unlikely to be backported to the v10 branch as it is the result of a significant rework of the parser.

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martinwhitaker
Joined:
2003-12-21 14:54:55

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