The latest patch fixes the bug when using the full original circuit. Thanks for the quick fix Giles.
If you have a patch, I can build and test locally.
You are right, the problem occurs when there are models at more than one level of the hierarchy. Here is a cut down version of the code that demonstrates the problem * Bug 817 test case .subckt 74LVC245APW OE IN OUT VCC GND .MODEL MNEN NMOS LEVEL = 3 KP = 154E-6 .MODEL MPEN PMOS LEVEL = 3 KP = 63.7E-6 .SUBCKT LVCINVAN 2 3 50 60 MP1 3 2 50 50 MPEN W= 30U L=0.8U AD=35P AS=35P PD=35U PS=30U MN1 3 2 60 60 MNEN W= 12U L=0.8U AD=30P AS=30P PD=20U PS=15U .ENDS XINV 30 35 50 60 LVCINVAN .ends .model MR1...
Global models are not visible from with subcircuits
Packages which tries to create an instance of a class is not accepted by Icarus.
This is now fixed in the master branch.
Parameters defined in package not seen in Verilog module imported it
This is now fixed in the master branch. The fix is unlikely to be backported to the v10 branch as it is the result of a significant rework of the parser.